1. Field of the Invention
The invention relates in general to a memory controller, and more particularly to a memory controller applied to a double-data-rate dynamic random access memory (DDR DRAM).
2. Description of the Related Art
A double-data-rate dynamic random access memory (DDR DRAM), featuring a fast access speed and low costs, is a common temporary data storage component in a computer system or in an electronic device. With the continual evolvement of DDR DRAM, current computer systems or electronic devices are mostly equipped with a DDR generation-3 (DDR3) DRAM. An accessing unit, such as a central processing unit (CPU), a graphic processing unit (GPU) or other peripheral element, requires a memory controller to access the DDR3 DRAM.
With the progressing development of memory technologies, a DDR generation-4 (DDR4) DRAM has become available. However, memory address configurations of the DDR3 DRAM and the DDR4 DRAM are different. For example, a DDR3 DRAM address includes a bank address, a row address and a column address. According to the DDR4 DRAM specification, a DDR4 DRAM address includes a bank address, a bank group address, a row address and a column address. That is, compared to the DDR3 DRAM address, the DDR4 DRAM address additionally includes the bank group address.
Further, based on the DDR4 DRAM specification, there are more parameters that limit data access. Thus, in a DDR4 DRAM system, a memory controller needs a novel method for generating a memory address to effectively utilize the DDR4 DRAM.